Authors: Florian Wiedner, Jonas Andre, Paulo Mendes, Georg Carle

Authors: Sebastian Gallenmüller, Dominik Scholz, Henning Stubbe, Eric Hauser, Georg Carle

Authors: Johannes Zirngibl, Steffen Deusch, Patrick Sattler, Juliane Aulbach, Georg Carle, Mattijs Jonker

Authors: Fabian Franzen, Lion Steger, Johannes Zirngibl, Patrick Sattler

Authors: Sebastian Gallenmüller, Eric Hauser, Georg Carle

Authors: Florian Wiedner, Max Helm, Sebastian Gallenmüller, Georg Carle

Authors: Fabien Geyer, Steffen Bondorf

Time sensitive network applications, for example in intra-vehicular networks, aim to give predictable end-to-end latency guarantees. As a consequence, processing resources of involved host systems remain partially unused, because they are reserved for rare worst cases. This circumstance provides the opportunity to reduce dimensioning overheads by managing the load on the nodes flexibly within the network. In our proposed approach, a SmartNIC involving an FPGA-based load balancer achieves dynamic routing of flows whilst preserving end-to-end latency guarantees. A flow-oriented online network measurement component continuously supervises network traffic with regards to compliance to flow specifications and constraints such as bounded one-way delay, absence of packet loss and jitter. We use the supervisor to enhance forwarding decisions on the data plane. Initial evaluation yields a saving potential of around 30 percent. We showcase quick dynamic reconfiguration of the FPGA when triggered by real-time measurement of the one-way delay using realistic automotive network traffic.

Authors: Kilian Holzinger, Franz Biersack, Henning Stubbe, Angela Gonzalez Mariño, Abdoul Kane, Francesc Fons, Zhang Haigang, Thomas Wild, Andreas Herkersdorf, Georg Carle

Authors: Simon Bauer, Benedikt Jaeger, Max Reimann, Jonas Fromm, Georg Carle

Authors: Lars Wüstrich, Sebastian Gallenmüller, Marc-Oliver Pahl, Georg Carle